Integrated circuits typically comprise a semiconductor substrate and semiconductor devices, such as transistors, comprising doped regions within the substrate. Interconnect structures overlie the semiconductor substrate for electrically connecting the doped regions to form electrical devices and circuits. Conventional interconnect structures comprise dielectric layers alternating with conductive layers. Substantially vertical conductive vias or plugs in the dielectric layers connect substantially horizontal conductive traces or runners in the conductive layers.
A CMOS device (complimentary metal-oxide semiconductor field effect transistor) comprises an n-channel and a p-channel metal-oxide semiconductor field effect transistor (MOSFET) formed in oppositely-doped adjacent wells. Each MOSFET further comprises source and drain regions separated by a channel, a gate oxide formed over the channel and a doped polysilicon gate electrode formed over the gate oxide. An appropriate gate voltage inverts the channel to permit current flow between the source and the drain regions.
Within an integrated circuit substrate, it may be necessary to electrically isolate certain doped regions to avoid the effects of parasitic devices that are formed by the undesired interaction of doped regions. For example, a parasitic bipolar structure, e.g., a p-n-p-n thyristor, is formed by the wells and the doped source/drain regions of a CMOS device. The thyristor is inoperative (off) under normal CMOS operating conditions. However, under certain bias conditions the p-n-p regions supply base current to the n-p-n regions, causing leakage current flow between the two MOSFETS of the CMOS device that can cause latch-up of the CMOS device. Isolation structures are conventionally formed within the substrate between adjacent MOSFETS to prevent this leakage current.
An oxide (silicon dioxide) isolation region, formed according to a local oxidation of silicon (LOCOS) process or according to a shallow trench isolation (STI) process, electrically isolates doped regions of adjacent transistors (or other devices formed in the integrated circuit) to minimize leakage current and reduce the aforementioned parasitic effects.
The local oxidation of silicon process forms recessed LOCOS isolation regions in non-active areas (field regions) of the semiconductor substrate. According to one LOCOS process, a layer of silicon nitride is deposited over the substrate and patterned according to conventional masking and etching steps to form openings in the silicon nitride that expose underlying semiconductor substrate regions. The isolating LOCOS regions are formed by oxidizing the exposed semiconductor substrate through the openings. No oxidation occurs in the regions masked by the silicon nitride.
An STI structure comprises a dielectric-filled substrate trench (about 300 nm deep) for electrically isolating active devices. Shallow trench isolation structures enjoy certain advantages over LOCOS structures as the STI structures consume less substrate surface area and exhibit a flatter upper surface topography. The reduced area consumption permits the circuit designer to include more transistors per unit area in the integrated circuit. The flatter upper surface topography is beneficial for forming properly dimensioned overlying material layers and for accurate photolithographic patterning.
STI structures, which are especially useful for device sizes below about 0.25 microns, also provide superior isolation because sharp corners formed at the bottom of the STI trench create voltage barriers that tend to block leakage currents between adjacent doped regions. LOCOS regions generally present rounded corners and thus may permit some leakage current.
FIGS. 5-8 are cross-sectional views across a common plane (not drawn to scale) illustrating successive prior art processing steps for forming a shallow trench isolation structure in a substrate of one integrated circuit of a plurality of integrated circuits formed on a wafer.
A semiconductor substrate 30 in FIG. 5 comprises spaced-apart doped regions 32. It is desired to isolate the doped regions 32 with a shallow trench isolation structure therebetween. A stress-reducing silicon dioxide layer 36 (also referred to as a pad oxide layer 36) is deposited or grown over an upper surface 37 of the substrate 30. Next, a silicon nitride layer 38 is deposited (typically according to a low pressure chemical vapor deposition process) over the silicon dioxide layer 36.
A photoresist layer 40 is deposited, exposed and developed according to known processes to form an opening 41 therein.
An opening 46 with sidewalls 47 is formed in the silicon nitride layer 38 and the pad oxide layer 36 through the opening 41. The opening 46 is preferably formed using a plasma etching process employing oxygen and a fluorine-containing gas, such as C2F6 and/or CHF3 (the fluorine-containing gas is selective to the silicon substrate 30).
The photoresist layer 40 is removed and the wafer is cleaned. Using the opening 46 as a mask, a trench 48 (see FIG. 6) with sidewalls 49 is formed in the semiconductor substrate 30 during an etching step, conventionally comprising a plasma dry etch using hydrogen bromide and chlorine.
A dielectric liner film 50 is formed or deposited in the trench 48.
As illustrated in FIG. 7, an STI structure 55 is formed by depositing dielectric material in the trench 48. The material deposition comprises a first step wherein a relatively low density dielectric material 56A is deposited within the trench 48 substantially adjacent the liner film 50. During a second deposition (bulk deposition) step, sufficient power is supplied to the deposition chamber to form a high ion density, which increases the material deposition rate (and the process throughput) to form a high-density dielectric material 56B (e.g., undoped silicate glass) in the trench 48. Typically the latter deposition is performed according to a high-density plasma undoped silicate glass deposition process (HDP USG). In another embodiment an atmospheric chemical vapor deposition process (APCVD) can be used in lieu of the HDP USG process. To deposit the high-density HDP USG material 56B, a plasma ion density in a range of about 1011 to about 1013 ions/cm3 is created within the deposition chamber, causing a relatively high material deposition rate and formation of the high-density material.
During the deposition step, dielectric material is also deposited on an upper surface 59 of the silicon nitride layer 38. A chemical-mechanical polishing (CMP) step removes the dielectric material from the upper surface 59, stopping on the silicon nitride layer 38. Since the CMP polishing rate for the dielectric material (e.g., HDP USG) is greater than the CMP polishing rate for silicon nitride, an upper surface 60 of the STI structure 55 is recessed below the upper surface 59 of the silicon nitride layer 38.
To complete formation of the STI structure 55, the wafer is cleaned according to a hydrofluoric (HF) clean process, the silicon nitride layer 38 and the pad oxide layer 36 are removed using known processes, such as an HF wet etch, and finally the wafer is cleaned again. FIG. 8 illustrates the structural elements of the STI structure 55, including sidewalls 62, following completion of these processing steps. For convenience, the low-density dielectric material 56A and the high-density dielectric material 56B are not separately depicted.
During the wet etch process to remove the silicon nitride layer 38 and the pad oxide layer 36, voids 70 (see FIG. 8) form at an interface between the low-density dielectric material and the high-density dielectric material.
During later deposition of a gate polysilicon layer, undesired polysilicon stringers (referred to as “wrap-ups”) can form around the sidewalls 62 and in the voids 70. The stringers may create short circuits or leakage current paths that defeat the STI isolation function, degrading performance of the integrated circuit, resulting in reliability issues and device failures. A process scheme that prevents void formation at the interface is desired.
In an effort to reduce a width and a depth of the voids 70 (and thus the likelihood that polysilicon stringers will form), it is known to shorten a duration of the cleaning step (typically a hydrofluoric acid clean) that follows the wet etch process for removing the silicon nitride layer 38 and the pad oxide layer 36. However, it is also known that a shorter clean may cause nitride residues and contaminants to remain on the substrate 30, possibly causing undesirable short circuits or leakage currents within the STI structure 55 and the substrate 30.